In recent years the C-to-HDL efficiencies have improved significantly. Most vendors quote 15% inefficiency, meaning the resulting circuit may consume around 15% more transistors, run slower, etc. But by some measurements they actually rival the ability of what a team of small humans could possibly do in a short amount of time (2-3 months). If youâ(TM)re prototyping or implementing the final thing on an FPGA Xilinx and Intel both have tools that compile from C and C++ into HDL (Verilog or VHDL) functional IP blocks. Iâ(TM)m careful to say âoeIP blocksâ because the resulting output is not very human readable, and it is more a convenience that it can be compiled by existing ASIC development tools that expect Verilog or VHDL input. Other commercial tools such as Mentor Graphics Catapult are very expensive, but can generate code that is useful for any vendor FPGA or production ASIC use. Catapult is also much more clever about the way it builds circuits by exploiting shared resources/data signals and multiplexing between various parts of an implemented algorithm to minimize the size of the resulting circuitry. The most important thing to realize about it all âoeC to gatesâ tools is that they arenâ(TM)t magical software to ASIC converters. They are good at taking a very raw algorithm that works on a data input, crunches it, and produces a data output. If your algorithm has unbounded recursion or needs access to gigabytes of RAM, then you will likely need to make some heavy modifications. This would be a similar exercise to the process taken to prepare code for a GPU offload (CUDA or OpenCL). And then the implemented âoeIP blockâ will need to be integrated into a larger ASIC design that schedules the I/O actions... And then the old-fashioned approach is to simply give a team of HDL designers access to your C source and the theory of operation. Then they spend a number of months or years carefully understanding the code and re-writing the logical operations and behavior in Verilog or VHDL. They take their time to optimize the computations done on each clock cycle, and carefully pipeline the design so the physical circuit implementation can execute at the desired frequency (MHz). Without knowing what the algorithm to be implemented is, it can be difficult to estimate the amount of time needed for ASIC implementation. If youâ(TM)re working with trigonometric functions and complex conjugateâ(TM)s for example, itâ(TM)s going to be significantly more work than caring out a bunch of logical operators and basic arithmetic. Hope this helps get you oriented!