So I am a digital engineer who writes a lot of VHDL from scratch to target both FPGAs and ASICs. Due to the cost, we always prototype on FPGAs first because mistakes are just too expensive. What you are asking for does not really exist. In C, you are defining a serial operation. Duplicating that exact process in an FPGA or ASIC makes no sense because there is nothing to gain. Your algorithm needs to be broken up into multiple parallel paths. FPGAs and ASICs are just digital circuits that you get to create and you can make everything be done in parallel if you are able to break up the process. Once you have broken up the process, then you can then target a GPU using openCL or CUDA. If you really want to go the FPGA/ASIC route, then Mathwork's Simulink (which also makes MATLAB) can be used to generate VHDL. SImulink's HDL coder does a pretty good job, but it will make unreadable code, but who cares as long as you have a functional product. Once you have the VHDL code, you can then see how many resources you will need. For FPGAs, sounds like you might need something with a lot of DSP elements (provides hardware multiplies and division). Downside is that you need to learn another tool which is Simulink. If your algorithm is simple, you could write it straight VHDL, but honestly, that is a huge pain in the ass. Get a prototype working first, optimize later.