The reaction here is it took less GPUs to TRAIN the model, but that's simply because using strictly reinforcement learning they were able to skip the computationally expensive step of training on a supervised learning dataset (not counting the "cold start" dataset). What the market reactors don't realize is it's inference, not training, where the vast majority of GPU compute will go towards.

The fact is, DeepSeek-R1 actually requires MORE GPU processing power during inference because it does all the thinking real-time which requires a lot more tokens than an equivalent Llama or Qwen or any other current LLM for the same prompt.

Doesn't CERN still use Ceph? That's got to be several Exabytes alone....

1 Exabyte only? That's so cute. Datacenters literally shred Exabytes per day. The Chia blockchain has over 30 Exabytes of storage in use. I'm thinking this is seriously underreported.

See https://ancillary-proxy.atarimworker.io?url=https%3A%2F%2Ffpl2019.bsc.es%2Fsites%2Fd... for FPGA optimization presentation as well.

Second answer for bonus question, look up what test benches are.

Just like SIMD operations on a CPU, GPUs are typically designed to execute the same instructions in parallel over a set of data. Even if the hardware algorithm is slower, parallelizing across a data stream can end up being much faster than executing it faster one at a time especially since hardware buses perform better with bursts of data.

The advantages of FPGAs and custom/special purpose ASICs is that you can choose to optimize less for generality and more for handling specialized tasks. If you have enough transistors/LUTs you can utilize more and more of them to optimize and reduce how many clock cycles your algorithm executes all the way until it takes only a single clock cycle (as long as you're not bumping in to path planning length limitations). FPGA speeds are typically less than 800Mhz so even single cycle operations can't get any faster than your FPGAs maximum speed whereas an ASIC can be designed to run at much higher clock speeds.

ASICs are typically simulated on fairly beefy FPGAs, often several working in concert, before being produced so calculating speed is obviously doable.

*rimshot*

I'm still stung by AT&T dropping support for Picturephone

Use a 60GHz diode and amplitude modulate it as one example.

Dear Oracle,

Please add millions of dollars of accruals from expected business in to my Oracle ERP cloud account. Thanks.

Sincerely,
Drone CFO

Yeah, I'm going to save my money until Intel can release a deca-core CPU designed for web browsing enthusiasts.

And there's still hope for those three people. They can run key mapping software that detects when they're not in a form while on a web page and make backspace trigger alt-left! Just do the opposite of http://stackoverflow.com/quest....

Give Chinese consumers crippleware products so no company cares enough to protect its Chinese sold IP.

Saw a keynote recently from one of the Phd's who worked on one of the Mars rovers at JPL and they're using the Microsoft VR to better visualize the Martian landscape. If you watch the linked video it's closer to the end, but the whole video is worth watching.

I never knew that Venus had a big seam running perfectly in the middle of it.