I just want to add some information I picked up regarding the Merced. I heard that the chip is extremely near tape-out. The person who said this was NOT specific regarding the exact time, but the implication was within the next two months or so. The validity of rumors are, as always, dependent on who supplies them, and I heard this at a lecture given by Frank Baetke (Manager of High-Performance Computing Technologies, Hewlett-Packard Gremany/USA) at the HiPer'99 conference. He should have access to the correct information from Intel, since Intel and HP are more or less bedmates when it comes to the IA-64 technology and implementation.

When it comes to the sucess/faliure of the Merced, keep in mind that the Merced has to/should implement the new all-cool speed increasing stuff that Intel shoves into the PIII (and beyond), and not only the entierly new stuff as the Merced must show off. Also getting VLIW to work is very much a matter of getting the compilers 'in tune' with the chip. Much more so with VLIW than ordinary RISC/CISC CPU's.

Secondly, keep in mind that IA-64 isn't a pure VLIW implemetation, it is also possible to run normal/sequential code on it as well (although it will probably be optimised for parallel code, duh). In the lecture that followed Yale Patt decribed the IA-64 as VLIW-when-you-need-it, more or less the best of both worlds, if done right. (If you don't know who Yale Patt is then you had better freshen up on your prosessor architecture knowledge!) He also seemed quite enthusiastic about the IA-64, or as enthusiastic as a guru can become of a commecial design. :)