Lines of C code or kB of compiled C code doesn't have any relation to the size/complexity/development cost of an ASIC.
Basically, you should constrain the problem by figuring out what the cost of the cheapest general purpose CPU and associated IO hardware would cost, and then figure what it would cost as a SoC by summing.
The ASIC, to be marketable, needs to either exceed that solution in performance or cost.
You should also look at the cost of ASICs that do similar work, possibly combining several if that's required. That gives you another estimate.
Writing your algorithm in verilog and programming an FPGA is a 3rd method.