SystemC Integrations

Coco is a comprehensive code coverage solution designed for modern software development across both embedded systems and desktop applications. It empowers developers, QA engineers, and compliance teams to measure and improve test coverage through function, branch, decision, condition, and MC/DC coverage metrics. With support for multiple languages and toolchains—including GCC, Clang, MSBuild, ARM, QNX, and Green Hills—Coco integrates seamlessly into existing CI/CD workflows without requiring code refactoring. Teams can quickly detect coverage gaps, streamline regression testing, and remove redundant test cases to shorten validation cycles. For regulated industries like automotive, aerospace, and healthcare, Coco delivers qualification kits and pre-built certification artifacts to support ISO 26262 and DO-178C compliance. The Coco Cross-Compilation Add-on extends capabilities to embedded Linux, RTOS, and bare-metal targets, offering full traceability from test execution to certification. Its integration with Test Center provides real-time analytics, visualization, and organization-wide reporting for test intelligence. With Coco, development teams gain transparency, speed, and trust in every release cycle.

ModelSim effectively simulates behavioral, RTL, and gate-level code, enhancing both design quality and debugging productivity through its platform-independent compilation. Its unique single kernel simulator technology allows for the seamless integration of VHDL and Verilog within a single design framework. This HDL simulator offers an unparalleled range of verification features at a competitive price, making it particularly suitable for the verification of small to medium-sized FPGA designs, especially those that are complex and mission-critical. ModelSim’s sophisticated code coverage tools yield essential metrics that aid in systematic verification processes. Additionally, its user-friendly design minimizes the obstacles to utilizing verification resources efficiently. All coverage data is securely stored in the highly efficient UCDB database, providing flexibility in how results can be accessed. Coverage outcomes can be analyzed interactively, either during or after simulation, including after merging results from multiple simulation sessions. This unified and easy-to-navigate environment equips FPGA designers with the necessary advanced tools for effective debugging and refinement of their projects.