Average Ratings 0 Ratings
Average Ratings 0 Ratings
Description
Questa Verification stands out as the pioneering platform that integrates a UVM-aware debug solution, equipping engineers with critical insights into the functionality of their dynamic class-based testbenches, all within the familiar environments of source code and waveform analysis. This verification suite encompasses a comprehensive collection of technologies, methodologies, and libraries tailored for contemporary ASIC and FPGA designs. As the complexity of System-on-Chip (SoC) designs escalates, Questa continuously adapts and enhances its offerings. The platform provides valuable insights and updates on key concepts, values, standards, and methodologies, along with practical examples that help users grasp the capabilities of advanced functional verification technologies and their optimal application. Additionally, the Verification Horizons publication serves as a vital resource, presenting crucial concepts, values, methodologies, and illustrative examples to deepen understanding and facilitate effective use of these cutting-edge verification tools. Through this ongoing commitment to innovation and education, engineers are better equipped to navigate the challenges of modern design verification.
Description
Our advanced web platform significantly enhances the productivity of chip developers and verification engineers, allowing them to design and troubleshoot at a pace ten times quicker than before. With Verilator, users can effortlessly initiate and execute thousands of tests simultaneously with just one click. It also facilitates the easy sharing of test outcomes and waveforms within the organization, allows for tagging colleagues on specific signals, and provides robust tracking of test and regression failures. By utilizing Verilator to create Dockerized simulation binaries, we efficiently distribute test executions across our computing cluster, after which we gather the results and log files and have the option to rerun any tests that failed to produce waveforms. The incorporation of Docker ensures that the test executions are both consistent and reproducible. SiLogy ultimately boosts the efficiency of chip developers by shortening the time required for design and debugging processes. Prior to the advent of SiLogy, the leading method for diagnosing a failing test entailed manually copying lines from log files, analyzing waveforms on personal machines, or rerunning simulations that could take an inordinate amount of time, often spanning several days. Now, with our platform, engineers can focus more on innovation rather than being bogged down by cumbersome debugging processes.
API Access
Has API
No
API Access
Has API
No
Pricing Details
No price information available.
Free Trial
No
Free Version
No
Pricing Details
No price information available.
Free Trial
No
Free Version
No
Deployment
Web-Based
No
On-Premises
No
iPhone App
No
iPad App
No
Android App
No
Windows
No
Mac
No
Linux
No
Chromebook
No
Deployment
Web-Based
Yes
On-Premises
No
iPhone App
No
iPad App
No
Android App
No
Windows
No
Mac
No
Linux
No
Chromebook
No
Customer Support
Business Hours
No
Live Rep (24/7)
No
Online Support
Yes
Customer Support
Business Hours
No
Live Rep (24/7)
No
Online Support
Yes
Types of Training
Training Docs
Yes
Webinars
Yes
Live Training (Online)
No
In Person
No
Types of Training
Training Docs
No
Webinars
No
Live Training (Online)
Yes
In Person
No
Vendor Details
Company Name
Siemens
Founded
1947
Country
United States
Website
eda.sw.siemens.com/en-US/ic/questa/simulation/
Vendor Details
Company Name
SiLogy
Founded
2023
Country
United States
Website
silogy.io
Product Features
Simulation
1D Simulation
No
3D Modeling
No
3D Simulation
No
Agent-Based Modeling
No
Continuous Modeling
No
Design Analysis
No
Direct Manipulation
No
Discrete Event Modeling
No
Dynamic Modeling
No
Graphical Modeling
No
Industry Specific Database
No
Monte Carlo Simulation
No
Motion Modeling
No
Presentation Tools
No
Stochastic Modeling
No
Turbulence Modeling
No
Product Features
PCB Design
3D Visualization
No
Autorouting
No
Collaboration Tools
No
Component Library
No
Design Rule Check
No
Differential Pair Routing
No
Schematic Editor
No