Average Ratings 0 Ratings
Average Ratings 0 Ratings
Description
Seamlessly repair damaged copper regions during interactive editing sessions, allowing for easy refinement of user-defined design selections. Components and enclosures can be moved within the 3D space while enjoying real-time clash detection for any violations. When faced with specific technological demands, you can take advantage of cutting-edge features like flexi-rigid design, embedded components, and chip-on-board technology to fulfill your functional needs. Pulsonix simplifies the process of generating a comprehensive Bill of Materials (BOM), pick and place lists, PCB acceptance reports, and netlists in various formats, whether you choose to use our pre-defined options or design your own. A standout feature of Pulsonix is the use of construction lines, which allow users to define guiding lines within their design, facilitating the creation of complex board outlines and aligning unconventional shapes or items. Additionally, you can establish rules for the automatic generation of naming conventions for both new and existing styles, enhancing organization and consistency in your design process. This comprehensive approach ensures that users can achieve a high level of precision and efficiency in their design workflows.
Description
Our advanced web platform significantly enhances the productivity of chip developers and verification engineers, allowing them to design and troubleshoot at a pace ten times quicker than before. With Verilator, users can effortlessly initiate and execute thousands of tests simultaneously with just one click. It also facilitates the easy sharing of test outcomes and waveforms within the organization, allows for tagging colleagues on specific signals, and provides robust tracking of test and regression failures. By utilizing Verilator to create Dockerized simulation binaries, we efficiently distribute test executions across our computing cluster, after which we gather the results and log files and have the option to rerun any tests that failed to produce waveforms. The incorporation of Docker ensures that the test executions are both consistent and reproducible. SiLogy ultimately boosts the efficiency of chip developers by shortening the time required for design and debugging processes. Prior to the advent of SiLogy, the leading method for diagnosing a failing test entailed manually copying lines from log files, analyzing waveforms on personal machines, or rerunning simulations that could take an inordinate amount of time, often spanning several days. Now, with our platform, engineers can focus more on innovation rather than being bogged down by cumbersome debugging processes.
API Access
Has API
API Access
Has API
Integrations
Accel Robotics
Allegro X Design Platform
Altium Designer
CR-8000 Design Force
CoolSpools
DesignSpark Electrical
Docker
Eagle
Gerber AccuMark 3D
GitHub
Integrations
Accel Robotics
Allegro X Design Platform
Altium Designer
CR-8000 Design Force
CoolSpools
DesignSpark Electrical
Docker
Eagle
Gerber AccuMark 3D
GitHub
Pricing Details
No price information available.
Free Trial
Free Version
Pricing Details
No price information available.
Free Trial
Free Version
Deployment
Web-Based
On-Premises
iPhone App
iPad App
Android App
Windows
Mac
Linux
Chromebook
Deployment
Web-Based
On-Premises
iPhone App
iPad App
Android App
Windows
Mac
Linux
Chromebook
Customer Support
Business Hours
Live Rep (24/7)
Online Support
Customer Support
Business Hours
Live Rep (24/7)
Online Support
Types of Training
Training Docs
Webinars
Live Training (Online)
In Person
Types of Training
Training Docs
Webinars
Live Training (Online)
In Person
Vendor Details
Company Name
Pulsonix
Website
pulsonix.com/pcb-design
Vendor Details
Company Name
SiLogy
Founded
2023
Country
United States
Website
silogy.io
Product Features
PCB Design
3D Visualization
Autorouting
Collaboration Tools
Component Library
Design Rule Check
Differential Pair Routing
Schematic Editor
Product Features
PCB Design
3D Visualization
Autorouting
Collaboration Tools
Component Library
Design Rule Check
Differential Pair Routing
Schematic Editor